The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device suitable for a MOS static random access memory (SRAM) for realizing high speed access to cells.
FIG. 1 shows a prior-art semiconductor memory, in which only the data-read related portion is shown in detail. In the drawing, CG denotes a cell group. Cells C (C11, C21, C31, . . . ; C12, C22, C32, . . . ; . . . ) of the cell group CG are connected to word lines WL (WL1, WL2, selected by a row address A1, respectively. Outputs of these cells C are read out through bit lines BL, BL (BL1, BL1; BL2, BL2; . . . ). Data of the bit lines BL, BL are transmitted to two I/O lines IOL (IOL1, IOL2) via column switches CSW (CSW1, CSW2, . . . ). Gates of these column switches CSW are connected to address lines AL (AL1, AL2, . . . ) selected by a column address A2, respectively. Further, two I/O lines IOL1 and IOL2 are connected to a sense amplifier SA. Sense outputs d, d are outputted from the sense amplifier SA and then given to an output buffer circuit OB. Two output gate lines G0 and G0 of the output buffer circuit OB are connected to gates of two series-connected output buffer transistors Q17 and Q18, respectively. An output signal D.sub.out can be obtained through a junction point between the two output buffer transistors Q17 and Q18.
The data reading operation of the prior-art memory device as described above will be ,described hereinbelow. When a word line WL1, for instance is selected by a row address A1, data are outputted from the cells C11, C21, . . . to the bit lines BL1, BL1; BL2, BL2; . . . . On the other hand, if an address line AL1 (column switch CSW1), for instance is further selected by a column address A2, a data of the cell C11 is transmitted to the I/O line IO1, amplified by the sense amplifier SA, and then given to the output buffer circuit OB as two sense outputs d, d, so that the outputs of the output buffer circuit OB are given to the gates of the two output buffer transistors Q17 and Q18 via the output gate lines G0, G1, respectively to generate a data of cell C11 as an output signal D.sub.out.
Thereafter, when the row address changes and therefore another word line WL2, for instance is selected, data of the cells C12, C22 . . . are transmitted to the bit lines BL1, BL1; BL2, BL2; . . . Further, if the column address A2 changes and therefore another address line AL2 (column switch CSW2), for instance is selected, a data of the cell 22 is transmitted to the I/O line IOL. In the same way as already described, a data of cell 22 is obtained from the junction point between the two transistors Q17 and Q18 as an output signal D.sub.out.
As described, in the prior-art semiconductor memory device, since the data read-out routes are all formed in the same way and therefore data are read from the respective cells via the same routes, respectively, the respective access times for reading data from the respective cells are roughly equal to each other. Therefore, it is extremely difficult to operate the memory unit (e.g. cash memory) in such a way that an access time on the basis of a specific address becomes shorter than that on the basis of the ordinary address.